1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having a multi-level interconnect structure in which lower-level interconnects (first-level interconnects) and upper-level interconnects (second-level interconnects) are electrically connected by via plugs embedded in via holes, and a method for manufacturing the semiconductor device.
2. Description of the Related Art
A process which comprises embedding a metal (electrical conductor) in interconnect trenches and via holes (so-called dual damascene process) is coming into practical use as a process for forming multi-level interconnects in manufacturing of a semiconductor device. According to this process, aluminum, or more recently a metal such as copper, silver, or the like, is embedded in interconnect trenches and via holes which have previously been formed in an interlevel dielectric layer formed on a semiconductor substrate, and then extra metal is removed by chemical-mechanical polishing (CMP) to flatten a surface of the substrate.
With respect to interconnects formed by such a process, for example, copper interconnects formed by using copper as an interconnect material, and surfaces of copper interconnects are exposed after performing a flattening process. In order to prevent thermal diffusion of the interconnects (copper), or to prevent oxidation of the interconnects (copper), for example, when superimposing thereon an insulating film (oxide film) in an oxidizing atmosphere to manufacture a semiconductor device having a multi-level interconnect structure, it is generally practiced to form a barrier layer (protective layer for interconnects) of SiN, SiC or the like not only on an interconnect region where the interconnects are exposed on a surface, but on an entire surface of the substrate.
FIG. 11 shows a general construction of a conventional multi-level interconnect structure of copper interconnects which are formed by using a dual damascene process. As shown in FIG. 11, interconnect trenches 14 are formed, for example, by performing a lithography/etching technique, in an insulating film (interlevel dielectric layer) 12 of, for example, SiO2 or a low-k material deposited on an insulating film 11 formed in a surface of a semiconductor substrate 10 having semiconductor devices formed therein. A barrier layer (diffusion preventing layer) 16 of TaN or the like is formed on the insulating film 12. Copper is embedded in the interconnect trenches 14 to form first-level copper interconnects (lower-level interconnects) 18, and a barrier layer (protective layer for interconnects) 20 of SiN or the like is formed on an entire surface, including exposed surfaces of the copper interconnects 18, to thereby form a first-level interconnect structure (lower-level interconnect structure).
The copper interconnects 18 are formed by performing copper plating to fill the interconnect trenches 14 with copper and deposit copper on the insulating film 12, followed by chemical-mechanical polishing (CMP) to remove extra copper and extra portions of the barrier layer on the insulating film 12 so as to make a surface of copper filling the interconnect trenches 14 substantially flush with a surface of the insulating film 12.
On an upper surface of the semiconductor substrate 10, having the first-level interconnect structure, is deposited an insulating film (interlevel dielectric layer) 22 of, for example, SiO2 or a low-k material. Via holes 24, reaching the first-level interconnects 18, and interconnect trenches 26 which are continuous with the via holes 24, are formed, for example, by performing a lithography/etching technique, in the insulating film 22. A barrier layer (diffusion preventing layer) 30 of TiN or the like is formed on the insulating film 22. Copper is embedded in the via holes 24 and the interconnect trenches 26 to form second-level copper interconnects (upper-level interconnects) 32 and via plugs 34 which electrically connect the copper interconnects 32 with the first-level copper interconnects 18. Then, a barrier layer (protective layer for interconnects) 36 of SiN or the like is formed on an entire surface, including exposed surfaces of the copper interconnects 32, to thereby form a second-level interconnect structure (upper-level interconnect structure).
As with the copper interconnects 18, the copper interconnects 32 are formed by performing copper plating, followed by chemical-mechanical polishing (CMP) to remove extra portions of a metal film for flattening of a surface.
It is also generally practiced to heat-treat (anneal) copper interconnects (copper plated film), prior to polishing away extra portions of the metal film by CMP, to recrystallize the copper interconnects.
With a conventional multi-level interconnect structure formed by using a dual damascene process, however, it is generally difficult to embed an interconnect material, such as copper, in via holes and interconnect trenches uniformly without mottles by, for example, electroplating. As shown in FIG. 11, voids V can be formed in the holes and trenches, which lowers a reliability of the interconnects and increases a resistance of the interconnects. It is thus difficult to establish a practical process. Further, embedding of interconnect material is generally performed by electroplating and, in this case, a copper seed layer is formed on a surface of a barrier layer in advance of the electroplating. Such a copper seed layer is generally formed by PVD or CVP, which employs a costly vacuum technology, that results in an increased cost. Further, as interconnects become finer, formation of a thin film seed layer having a uniform thickness is generally becoming difficult.
Further, when the barrier layer 20 of SiN or the like, as a protective film for interconnects, is formed on the entire surface of the substrate, dielectric constant k of the barrier layer 20 is generally higher than dielectric constant k of common interlevel dielectric layers 12, 22. A difference in this dielectric constant is marked especially when a low-k material is used for the interlevel dielectric layers 12, 22, and the dielectric constant of the interlevel dielectric layers as a whole is increased, which includes interconnect delay. Even when a low-resistance material, such as copper or silver, is employed as an interconnect material, enhancement of performance of the semiconductor device will be impeded.
Furthermore, stress in interconnects and via plugs embedded in interconnect trenches and via holes cannot be reduced. This can cause electromigration (EM) or stress migration (SM), leading to lowering of reliability of the interconnects.